1. Field of the Invention
This invention relates to integrated circuits (ICs) comprising a substrate carrying a large number of circuit elements such as transistors and the like. More particularly, this invention relates to ICs having means to reduce damage from the effects of electrostatic discharge (ESD).
2. Prior Art
It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Discharge (ESD) events. The electrostatic voltage associated with the discharge can be developed by any of many sources, such as lighting, or friction between insulating bodies such as synthetic fiber clothing. Damage occurs when the ESD voltage is accidentally coupled to one of the circuit terminals and thence to some portion of the metal interconnect layer of the IC.
The metal interconnect is typically an Aluminum layer laid down over an oxide coating overlying the top surface of the semiconductor. The ESD voltage can cause a current to flow from the metal through the normally nonconducting oxide coating to the underlying semiconductor. The current then leaves the IC through some other circuit terminal. The magnitude of the current is often sufficient to cause significant damage to the oxide, particularly by leaving it permanently conducting. The resulting shunt pasth often causes circuit failure.
Various attempts have been made to prevent damage from ESD events. For example, semiconductor elements which require thin oxides, such as MOS transistors and MOS capacitors, are often protected by additional devices which bypass the ESD current and thereby protect the element in question. In general, a separate bypass device must be provided for each element requiring protection. However, in some particular cases the protection device may be shared by more than one element requiring protection. In any event, providing protection devices to prevent damage from ESD events adds to the complexity of the IC, requires additional IC area, and generally is a quite undesirable practice.
Many ICs are made with semiconductive elements which, unlike MOS transitors, do not require thin oxides, for example bipolar transistors. These ICs nevertheless may as a result of the particular process steps carried out have thin oxides in certain places, or may have had the usual thermal oxide completely or almost completely removed in selected places, and are thus susceptible to ESD induced damage. This invention describes a process for use with such ICs which eliminates the need to provide specific protection devices in accordance with prior practice.